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ordering information/selector guide appears at end of data sheet. general description the max17245 high-efficiency, synchronous step-down dc-dc converter with integrated mosfets operates over a 3.5v to 36v input voltage range with 42v input transient protection. the max17245 can operate in drop - out condition by running at 98% duty cycle. this converter delivers up to 3.5a and generates fixed output voltages of 3.3v/5v, along with the ability to program the output voltage between 1v to 10v. the max17245 uses a current-mode control architecture and can operate in the pulse-width modulation (pwm) or pulse-frequency modulation (pfm) control schemes. pwm operation provides constant frequency operation at all loads and is useful in applications sensitive to switching frequency. pfm operation disables negative inductor current and additionally skips pulses at light loads for high efficiency. under light-load applications, the external sync pin fsync logic input allows the device to operate in either pfm mode for reduced current consumption or fixed-frequency pwm (forced-pwm) mode to eliminate frequency variation to minimize emi. fixed-frequency pwm mode is extremely useful for power supplies designed for rf transceivers where tight emission control is necessary. this device is available in a compact 16-pin (5mm x 5mm) tqfn package with exposed pad and 16-pin tssop. -40c to +85c operation. benefts and features eliminates external components and reduces total cost ? integrated high-side and low-side switch enables synchronous operation for high effciency and reduced cost ? all-ceramic capacitor solution allows ultra-compact solution size ? 220khz to 2.2mhz adjustable frequency with external synchronization ? power good output and high-voltage en input simplify power sequencing increases design flexibility ? 180 out-of-phase clock output at syncout enables cascaded power supplies for increased power output ? fixed output voltage with 2% accuracy (5v/3.3v) or externally resistor adjustable (1v to 10v) reduces power dissipation ? >90% peak effciency ? pwm and pfm operation optimizes conversion effciency from heavy to light loads ? automatic lx slew-rate adjustment for optimum effciency across operating frequency range ? low 5a (typ.) shutdown current ? low 28a (typ.) quiescent current operates reliably ? 42v input voltage transient protection ? fixed 8ms internal software start reduces input inrush current ? cycle-by-cycle current limit, thermal shutdown with automatic recovery ? reduced emi emission with spread-spectrum control applications distributed supply regulation wall transformer regulation general-purpose point-of-load 19-8527; rev 0; 4/16 d1 c out 22f c in2 4.7f r comp 20ki r pgood 10ki r syncout 100i r fosc 12ki l1 2.2h v out 5v at 3.5a c bst 0.1f lx bst v out v bias out v bat fb v bias v out pgood syncout fosc c bias 1f c comp2 12pf bias c comp1 1000pf comp fsync osc sync pulse en supsw sup c in3 4.7f r ___ 0i c in1 power-good output 180 out-of-phase output agnd pgnd max17245 r snub* c snub* *r snub = 1i and c snub = 220pf required for the following operating conditions: v bat r 25v, v out p 5v, f sw r 1.8mhz, fpwm mode enabled typical application circuit max17245 3.5vC36v, 3.5a, synchronous buck converter with 28 a quiescent current and reduced emi evaluation kit available
tqfn junction-to-ambient thermal resistance ( b ja ) ........... 35oc/w junction-to-case thermal resistance ( b jc ) .............. 2.7oc/w tssop junction-to-ambient thermal resistance ( b ja ) ........ 38.3oc/w junction-to-case thermal resistance ( b jc ) ................. 3oc/w *as per jedec51 standard (multilayer board). sup, supsw, en to pgnd .................................. -0.3v to +42v lx (note 1) ............................................................ -0.3v to +42v sup to supsw .................................................... -0.3v to +0.3v bias to agnd ......................................................... -0.3v to +6v syncout, fosc, comp, fsync, pgood , fb to agnd ........................ -0.3v to (v bias + 0.3v) out to pgnd ....................................................... -0.3v to +12v bst to lx (note 1) .................................................. -0.3v to +6v agnd to pgnd ................................................... -0.3v to + 0.3v lx continuous rms current ................................................ 3.5a output short-circuit duration .................................... continuous continuous power dissipation (t a = +70c)* tqfn (derate 28.6mw/oc above +70c) ............... 2285.7mw tssop (derate 26.1mw/oc above +70c) ............ 2088.8mw operating temperature range ....................... -40c to +85c junction temperature ...................................................... +150c storage temperature range ............................ -65c to +150c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c (v sup = v supsw = 14v, v en = 14v, l1 = 2.2 h, c in = 4.7f, c out = 22f, c bias = 1f, c bst = 0.1f, r fosc = 12k, t a = t j = -40 c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 3) parameter symbol conditions min typ max units supply voltage v sup , v supsw 3.5 36 v line transient event supply voltage v sup_t_lt t t_lt < 1s 42 v supply current i sup_standby standby mode, no load, v out = 5v, v fsync = 0v 28 40 a standby mode, no load, v out = 3.3v, v fsync = 0v 22 35 shutdown supply current i shdn v en = 0v 5 10 a bias regulator voltage v bias v sup = v supsw = 6v to 42v, i bias = 0 to 10ma 4.7 5 5.4 v bias undervoltage lockout v uvbias v bias rising 2.95 3.15 3.40 v bias undervoltage lockout hysteresis 450 650 mv thermal shutdown threshold +175 c thermal shutdown threshold hysteresis 15 c package thermal characteristics (note 2) absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: self-protected against transient voltages exceeding these limits for 50ns under normal operation and loads up to the maximum rated output current. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . electrical characteristics maxim integrated 2 www.maximintegrated.com max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi
(v sup = v supsw = 14v, v en = 14v, l1 = 2.2 h, c in = 4.7f, c out = 22f, c bias = 1f, c bst = 0.1f, r fosc = 12k, t a = t j = -40 c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 3) parameter symbol conditions min typ max units output voltage (out) pwm mode output voltage v out_5v v fb = v bias, 6v < v supsw < 36v, fxed-frequency mode (notes 4, 5) 4.9 5 5.1 v v out_3.3v 3.234 3.3 3.366 pfm mode output voltage v out_pfm_5v no load, v fb = v bias , pfm mode (note 6) 4.9 5 5.15 v v out_pfm_3.3v 3.234 3.3 3.4 load regulation v fb = v bias , 300ma < i load < 3.5a 0.5 % line regulation v fb = v bias , 6v < v supsw < 36v (note 5) 0.02 %/v bst input current i bst_on high-side mosfet on, v bst - v lx = 5v 1 1.5 2 ma i bst_off high-side mosfet off, v bst - v lx = 5v, t a = +25c 5 a lx current limit i lx peak inductor current 4.2 5.2 6.2 a lx rise time r fosc = 12k 4 ns pfm mode current threshold i pfm_th t a = +25c 200 400 500 ma spread spectrum spread spectrum enabled f osc 6% high-side switch on-resistance r on_h i lx = 1a, v bias = 5v 100 220 m high-side switch leakage current high-side mosfet off, v sup = 36v, v lx = 0v, t a = +25c 1 3 a low-side switch on-resistance r on_l i lx = 0.2a, v bias = 5v 1.5 3 low-side switch leakage current v lx = 36v, t a = +25c 1 a transconductance amplifier (comp) fb input current i fb 20 100 na fb regulation voltage v fb fb connected to an external resistor divider, 6v < v supsw < 36v (note 7) 0.99 1.0 1.015 v fb line regulation ?v line 6v < v supsw < 36v 0.02 %/v transconductance (from fb to comp) g m v fb = 1v, v bias = 5v 700 s minimum on-time t on_min (note 5) 80 ns maximum duty cycle dc max 98 % oscillator frequency oscillator frequency r fosc = 73.2k 340 400 460 khz r fosc = 12k 2.0 2.2 2.4 mhz electrical characteristics (continued) maxim integrated 3 www.maximintegrated.com max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi
note 3: limits are 100% production tested at t a = +25c. limits over the operating temperature range are guaranteed by design. note 4: device not in dropout condition. note 5: filter circuit required, see the typical application circuit. note 6: guaranteed by design; not production tested. note 7: fb regulation voltage is 1%, 1.01v (max), for -40c < t a < +105c. note 8: contact the factory for sync frequency outside the specified range. (v sup = v supsw = 14v, v en = 14v, l1 = 2.2 h, c in = 4.7f, c out = 22f, c bias = 1f, c bst = 0.1f, r fosc = 12k, t a = t j = -40 c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 3) parameter symbol conditions min typ max units external clock input (fsync) external input clock acquisition time t fsync 1 cycles external input clock frequency r fosc = 12k (note 8) 1.8 2.6 mhz external input clock high threshold v fsync_hi v fsync rising 1.4 v external input clock low threshold v fsync_lo v fsync falling 0.4 v soft-start time t ss 5.6 8 12 ms enable input (en) enable input high threshold v en_hi 2.4 v enable input low threshold v en_lo 0.6 enable threshold voltage hysteresis v en_hys 0.2 v enable input current i en t a = +25c 0.1 1 a power good ( pgood) pgood switching level v th_rising v fb rising, v pgood = high 93 95 97 %v fb v th_falling v fb falling, v pgood = low 90 92 94 pgood debounce time 10 25 50 s pgood output low voltage i sink = 5ma 0.4 v pgood leakage current v out in regulation, t a = +25c 1 a syncout low voltage i sink = 5ma 0.4 v syncout leakage current t a = +25c 1 a fsync leakage current t a = +25c 1 a overvoltage protection overvoltage protection threshold v out rising (monitored at fb pin) 105 % v out falling (monitored at fb pin) 102 electrical characteristics (continued) maxim integrated 4 www.maximintegrated.com max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi
(v sup = v supsw = 14v, v en = 14v, v out = 5v, v fysnc = 0v, r fosc = 12k , t a = +25c, unless otherwise noted.) supply current vs. supply voltage toc09 supply voltage (v) supply current (a) 26 16 15 20 25 30 35 40 45 50 10 63 6 5v/2.2mhz pfm mode switching frequency vs. r fosc toc08 r fosc (k ) switching frequency (mhz) 102 72 42 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 0 12 132 f sw vs. temperature toc07 temperature (c) f sw (mhz) 110 95 -25 -10 5 35 50 65 20 80 2.04 2.08 2.12 2.16 2.20 2.24 2.28 2.00 -40 125 v in = 14v, pwm mode v out = 5v 425 427 429 431 433 435 437 439 441 443 445 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 f sw (khz) i load (a) f sw vs. load current v in = 14v, pwm mode v out = 3.3v v out = 5v toc06 2.10 2.12 2.14 2.16 2.18 2.20 2.22 2.24 2.26 2.28 2.30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 f sw (mhz) i load (a) f sw vs. load current v in = 14v, pwm mode v out = 3.3v v out = 5v toc05 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v out (v) i load (a) v out load regulation v out = 5v, v in = 14v pwm mode 400khz 2.2mhz toc04 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v out (v) i load (a) v out load regulation v out = 5v, v in = 14v skip mode 400khz 2.2mhz toc03 0 10 20 30 40 50 60 70 80 90 100 0.0000 0.0010 0.1000 10.0000 efficiency (%) load current (a) efficiency vs. load current f sw = 400khz, v in = 14v skip mode pwm mode 3.3v 3.3v 5v 5v toc02 0 10 20 30 40 50 60 70 80 90 100 0.0000 0.0010 0.1000 10.0000 efficiency (%) load current (a) efficiency vs. load current f sw = 2.2mhz, v in = 14v skip mode pwm mode 3.3v 3.3v 5v 5v toc01 c t cttc maxim integrated 5 www.maximintegrated.com max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi
(v sup = v supsw = 14v, v en = 14v, v out = 5v, v fysnc = 0v, r fosc = 12k , t a = +25c, unless otherwise noted.) 10v/div 0v 5v/div 0v 2a/div 0v toc15 v in v out slow v in ramp behavior i load v pgood 5v/div 0v 10v/div 0v 5v/div 0v 1a/div 0v toc14 v in v out full - load startup behavior i load v pgood 5v/div 0v v out vs. v in toc13 v in (v) v out (v) 30 24 18 12 4.97 4.99 5.01 5.03 5.05 4.95 63 6 5v/400khz pwm mode i load = 0a v out vs. v in toc12 v in (v) v out (v) 36 30 24 18 12 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 4.90 64 2 5v/2.2mhz pwm mode i load = 0a v bias vs. temperature toc11 temperature (c) v bias (v) 110 95 65 80 -10 5 20 35 50 -25 4.91 4.92 4.93 4.94 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 4.90 -40 125 i load = 0a v in = 14v, pwm mode shdn current vs. supply voltage toc10 supply voltage (v) supply current (a) 30 24 18 12 1 2 3 4 5 6 7 8 9 10 0 63 6 5v/2.2mhz pfm mode typical operating characteristics (continued) maxim integrated 6 www.maximintegrated.com max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi
(v sup = v supsw = 14v, v en = 14v, v out = 5v, v fysnc = 0v, r fosc = 12k , t a = +25c, unless otherwise noted.) dips and drops test toc18 v in v out v lx v pgood 5v/2.2mhz 10ms 10v/div 0v 0v 5v/div 10v/div 0v 0v 5v/div sync function toc17 v lx v fsync 200ns 5v/div 2v/div line transient toc19 v in v out v pgood 400ms 2v/div 0v 2v/div 2v/div 200mv/ div 2a/ div 0a toc21 v out (ac_coupled) load current load transient (pwm mode) line transient toc20 v in v out 100ms 10v/div 0v 0v 5v/div short circuit in pwm mode toc22 v out inductor current 10ms 2v/div 0v 0v 5v/div 2a/div 0a v pgood typical operating characteristics (continued) maxim integrated 7 www.maximintegrated.com max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi
pin name function tqfn tssop 16 1 syncout open-drain clock output. syncout outputs 180 out-of-phase signal relative to the internal oscillator. connect to out with a resistor between 100 i and 1k for 2mhz operation. for low frequency operation, use a resistor between 1k and 10k. 1 2 fsync synchronization input. the device synchronizes to an external signal applied to fsync. connect fsync to agnd to enable pfm mode operation. connect to bias or an external clock to enable fxed-frequency forced pwm mode operation. 2 3 f osc resistor-programmable switching frequency setting control input. connect a resistor from f osc to agnd to set the switching frequency. 3 4 out switching regulator output. out also provides power to the internal circuitry when the output voltage of the converter is set between 3v to 5v during standby mode. 4 5 fb feedback input. connect an external resistive divider from out to fb and agnd to set the output voltage. connect to bias to set the output voltage to 5v. 5 6 comp error amplifer output. connect an rc network from comp to agnd for stable operation. see the compensation network section for more information. 6 7 bias linear regulator output. bias powers up the internal circuitry. bypass with a 1f capacitor to ground. 7 8 agnd analog ground 8 9 bst high-side driver supply. connect a 0.1f capacitor between lx and bst for proper operation. + tssop 13 4 lx out 14 3 lx fosc 15 2 pgnd fsync 16 1 top view pgood syncout 10 7 en bias 11 6 sup comp 9 8 bst agnd 12 5 supsw fb ep max17245 + ep 15 16 14 13 6 5 7 fosc fb 8 fsync supsw en lx 12 pgnd 4 12 11 9 syncout bst agnd bias comp out sup 3 10 lx tqfn pgood max17245 pin descriptions pin confgurations maxim integrated 8 www.maximintegrated.com max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi
detailed description the max17245 is a 3.5a current-mode, step-down con - verter with integrated high-side and low-side mosfets designed to operate with an external schottky diode for better efficiency. the low-side mosfet enables fixed- frequency forced-pwm (fpwm) operation under light- load applications. the device operates with input voltages from 3.5v to 36v, while using only 28a quiescent current at no load. the switching frequency is resistor programmable from 220khz to 2.2mhz and can be synchronized to an external clock. the output voltage is available as 3.3v/5v fixed or adjustable from 1v to 10v. the wide input voltage range, along with its ability to operate at 98% duty cycle during undervoltage transients, make this device ideal for many applications. under light-load applications, the fsync logic input allows the device to either operate in pfm mode for reduced current consumption or fixed-frequency pwm mode to eliminate frequency variation to minimize emi. fixed-frequency pwm mode is extremely useful for power supplies designed for rf transceivers where tight emission control is necessary. protection features include cycle-by- cycle current limit, overvoltage protection, and thermal shutdown with automatic recovery. additional features include a power-good monitor to ease power-supply sequencing and a 180 out-of-phase clock output relative to the internal oscillator at syncout to create cascaded power supplies with multiple devices. wide input voltage range the device includes two separate supply inputs (sup and supsw) specified for a wide 3.5v to 36v input voltage range. v sup provides power to the device and v supsw provides power to the internal switch. when the device is operating with a 3.5v input supply, conditions such as cold crank can cause the voltage at sup and supsw to drop below the programmed output voltage. under such conditions, the device operate in a high duty-cycle mode to facilitate minimum dropout from input to output. in applications where the input voltage exceeds 25v, output is 5v, operating frequency is 1.8mhz and the ic is selected to be in pwm mode by either forcing the fsync pin high, or using an external clock, pulse skipping is observed on the lx pin. this happens due to insufficient minimum on time. add optional r snub = 1 and c snub = 220pf to reduce ringing on the lx pin (see the typical application circuit ). linear regulator output (bias) the max17245 includes a 5v linear regulator (bias) that provides power to the internal circuit blocks. connect a 1f ceramic capacitor from bias to agnd. pin name function tqfn tssop 9 10 en sup voltage compatible enable input. drive en low to pgnd to disable the device. drive en high to enable the device. 10 11 sup voltage supply input. sup powers up the internal linear regulator. bypass sup to pgnd with a 4.7f ceramic capacitor. it is recommended to add a placeholder for an rc flter to reduce noise on the internal logic supply (see the typical application circuit ). 11 12 supsw internal high-side switch supply input. supsw provides power to the internal switch. bypass supsw to pgnd with 0.1f and 4.7f ceramic capacitors. 12, 13 13, 14 lx inductor switching node. connect a schottky diode between lx and pgnd. 14 15 pgnd power ground 15 16 pgood open-drain, active-low power-good output. pgood asserts when v out is above 95% regulation point. pgood goes low when v out is below 92% regulation point. ep exposed pad. connect ep to a large-area contiguous copper ground plane for effective power dissipation. do not use as the only ic ground connection. ep must be connected to pgnd. pin descriptions (continued) maxim integrated 9 www.maximintegrated.com max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi
power-good output ( pgood) this device features an open-drain power-good output, pgood. pgood asserts when v out rises above 95% of its regulation voltage. pgood deasserts when v out drops below 92% of its regulation voltage. connect pgood to bias with a 10k resistor. overvoltage protection (ovp) if the output voltage reaches the ovp threshold, the high- side switch is forced off and the low-side switch is forced on until negative-current limit is reached. after negative- current limit is reached, both the high-side and low-side switches are turned off. the max17245 offers a lower voltage threshold for applications requiring tighter limits of protection. figure 1. internal block diagram fbsw out c omp pgoo d en fb soft st ar t sl ope c omp fbok eamp hsd lsd ao n lo gic cs ref hvldo swit ch over pwm sup bias bst supsw lx pgnd sync out bias fsync f osc ag nd osc max17245 maxim integrated 10 www.maximintegrated.com max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi
synchronization input (fsync) fsync is a logic-level input useful for operating mode selection and frequency control. connecting fsync to bias or to an external clock enables fixed-frequency pwm operation. connecting fsync to agnd enables pfm mode operation. the external clock frequency at fsync can be higher or lower than the internal clock by 20%. ensure the duty cycle of the external clock used has a minimum pulse width of 100ns. the device synchronizes to the external clock within one cycle. when the external clock signal at fsync is absent for more than two clock cycles, the device reverts back to the internal clock. system enable (en) an enable control input (en) activates the device from its low-power shutdown mode. en is compatible with inputs from automotive battery level down to 3.5v. the high voltage compatibility allows en to be connected to sup, key/kl30, or the inhibit pin (inh) of a can transceiver. en turns on the internal regulator. once v bias is above the internal lockout threshold, v uvl = 3.15v (typ), the controller activates and the output voltage ramps up within 8ms. a logic-low to pgnd at en shuts down the device. during shutdown, the internal linear regulator and gate drivers turn off. shutdown is the lowest power state and reduces the quiescent current to 5a (typ). drive en high to bring the device out of shutdown. spread-spectrum option the device has an internal spread-spectrum option to optimize emi performance. this is factory set and the s-version of the device should be ordered. for spread- spectrum-enabled devices, the operating frequency is varied 6% centered on the oscillator frequency (f osc ). the modulation signal is a triangular wave with a period of 110s at 2.2mhz. therefore, f osc will ramp down 6% and back to 2.2mhz in 110s and also ramp up 6% and back to 2.2mhz in 110s. the cycle repeats. for operations at f osc values other than 2.2mhz, the modulation signal scales proportionally (e.g., at 400khz, the 110s modulation period increases to 110s x 2.2mhz/400khz = 605s). the internal spread spectrum is disabled if the device is synced to an external clock. however, the device does not filter the input clock and passes any modulation (including spread-spectrum) present on the driving external clock to the syncout pin. automatic slew-rate control on lx the device has automatic slew-rate adjustment that optimizes the rise times on the internal hsfet gate drive to minimize emi. the device detects the internal clock frequency and adjusts the slew rate accordingly. when the user selects the external frequency setting resistor r fosc such that the frequency is > 1.1mhz, the hsfet is turned on in 4ns (typ). when the frequency is < 1.1mhz the hsfet is turned on in 8ns (typ). this slew-rate control optimizes the rise time on lx node externally to minimize emi while maintaining good efficiency. internal oscillator (fosc) the switching frequency (f sw ) is set by a resistor (r fosc ) connected from f osc to agnd. see figure 3 to select the correct r fosc value for the desired switching frequency. for example, a 400khz switching frequency is set with r fosc = 73.2k. higher frequencies allow designs with lower inductor values and less output capacitance. consequently, peak currents and i 2 r losses are lower at higher switching frequencies, but core losses, gate charge currents, and switching losses increase. synchronizing output (syncout) syncout is an open-drain output that outputs a 180o out-of-phase signal relative to the internal oscillator. overtemperature protection thermal-overload protection limits the total power dissipation in the device. when the junction temperature exceeds 175c (typ), an internal thermal sensor shuts down the internal bias regulator and the step-down controller, allowing the device to cool. the thermal sensor turns on the device again after the junction temperature cools by 15c. maxim integrated 11 www.maximintegrated.com max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi
applications information setting the output voltage connect fb to bias for a fixed 5v output voltage. to set the output to other voltages between 1v and 10v, connect a resistive divider from output (out) to fb to agnd ( figure 2 ). use the following formula to determine the r fb2 of the resistive divider network: r fb2 = r total x v fb /v out where v fb = 1v, r total = selected total resistance of r fb1 , r fb2 in , and v out is the desired output in volts. calculate r fb1 (out to fb resistor) with the following equation: out fb1 fb2 fb v rr 1 v ?? ?? = ? ?? ?? ?? ?? ?? where v fb = 1v (see the electrical characteristics table). pwm/pfm modes this device offers a pin-selectable pfm mode or fixed- frequency pwm mode option. they have an internal ls mosfet that turns on when the fsync pin is connected to v bias or if there is a clock present on the fsync pin. this enables the fixed-frequency-forced pwm mode operation over the entire load range. this option allows the user to maintain fixed frequency over the entire load range in applications that require tight control on emi. even though the device has an internal ls mosfet for fixed- frequency operation, an external schottky diode is still required to support the entire load range. if the fsync pin is connected to agnd, the pfm mode is enabled on the device. in pfm mode of operation, the converters switching frequency is load dependent. at higher load current, the switching frequency does not change and the operating mode is similar to the pwm mode. pfm mode helps improve efficiency in light-load applications by allowing the converters to turn on the high-side switch only when the output voltage falls below a set threshold. as such, the converters do not switch mosfets on and off as often as is the case in the pwm mode. consequently, the gate charge and switching losses are much lower in pfm mode. refer to the rectifier selection section for pfm mode. inductor selection three key inductor parameters must be specified for operation with the device: inductance value (l), inductor saturation current (i sat ), and dc resistance (r dcr ). to select inductance value, the ratio of inductor peak-to-peak ac current to dc average current (lir) must be selected first. a good compromise between size and loss is a 30% peak-to-peak ripple current to average current ratio (lir = 0.3). the switching frequency, input voltage, output voltage, and selected lir then determine the inductor value as follows: out sup out sup sw out v (v v ) l v f i lir ? = where v sup , v out , and i out are typical values (so that efficiency is optimum for typical conditions). the switching frequency is set by r fosc (see figure 3). figure 2. adjustable output-voltage setting figure 3. switching frequency vs. r fosc switching frequency vs. r fosc r fosc (k ) switching frequency (mhz) 102 72 42 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 0 12 132 r fb2 r fb1 fb v out max17245 maxim integrated 12 www.maximintegrated.com max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi
input capacitor the input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuits switching. the input capacitor rms current requirement (i rms ) is defined by the following equation: out sup out rms load(max) sup v (v v ) ii v ? = i rms has a maximum value when the input voltage equals twice the output voltage (v sup = 2v out ), so i rms(max) = i load(max) /2. choose an input capacitor that exhibits less than +10c self-heating temperature rise at the rms input current for optimal long-term reliability. the input voltage ripple is composed of ?v q (caused by the capacitor discharge) and dv esr (caused by the esr of the capacitor). use low-esr ceramic capacitors with high ripple current capability at the input. assume the contribution from the esr and capacitor discharge equal to 50%. calculate the input capacitance and esr required for a specified input voltage ripple using the following equations: esr in l out v esr i i 2 ? = ? + where: sup out out l sup sw (v v ) v i v fl ? ?= and: out out in q sw supsw i d(1 d) v c and d vf v ? = = ? where i out is the maximum output current and d is the duty cycle. output capacitor the output filter capacitor must have low enough esr to meet output ripple and load transient requirements. the output capacitance must be high enough to absorb the inductor energy while transitioning from full-load to no- load conditions without tripping the overvoltage fault protection. when using high-capacitance, low-esr capacitors, the filter capacitors esr dominates the output voltage ripple. so the size of the output capacitor depends on the maximum esr required to meet the output voltage ripple (v ripple(p-p) ) specifications: ripple(p p) load(max) v esr i lir ? = the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value. when using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent voltage droop and voltage rise from causing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. however, low capacity filter capacitors typically have high esr zeros that can affect the overall stability. rectifer selection the device requires an external schottky diode recti - fier as a freewheeling diode when they are configured for pfm-mode operation. connect this rectifier close to the device, using short leads and short pcb traces. in pwm mode, the schottky diode helps minimize efficiency losses by diverting the inductor current that would otherwise flow through the low-side mosfet. choose a rectifier with a voltage rating greater than the maximum expected input voltage, v supsw . use a low forward- voltage-drop schottky rectifier to limit the negative voltage at lx. avoid higher than necessary reverse-voltage schottky rectifiers that have higher forward-voltage drops. maxim integrated 13 www.maximintegrated.com max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi
compensation network the device uses an internal transconductance error amplifier with its inverting input and its output available to the user for external frequency compensation. the output capacitor and compensation network determine the loop stability. the inductor and the output capacitor are chosen based on performance, size, and cost. additionally, the compensation network optimizes the control-loop stability. the controller uses a current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor. the device uses the voltage drop across the high-side mosfet to sense inductor current. current-mode control eliminates the double pole in the feedback loop caused by the inductor and output capacitor, resulting in a smaller phase shift and requiring less elaborate error-amplifier compensation than voltage-mode control. only a simple single-series resistor (r c ) and capacitor (c c ) are required to have a stable, high-bandwidth loop in applications where ceramic capacitors are used for output filtering ( figure 4 ). for other types of capacitors, due to the higher capacitance and esr, the frequency of the zero created by the capacitance and esr is lower than the desired closed-loop crossover frequency. to stabilize a nonceramic output capacitor loop, add another compensation capacitor (c f ) from comp to agnd to cancel this esr zero. the basic regulator loop is modeled as a power modulator, output feedback divider, and an error amplifier. the power modulator has a dc gain set by g m o r load , with a pole and zero pair set by r load , the output capacitor (c out ), and its esr. the following equations allow to approximate the value for the gain of the power modulator (gain mod(dc) ), neglecting the effect of the ramp stabilization. ramp stabilization is necessary when the duty cycle is above 50% and is internally done for the device. mod(dc) m load gain g r = where r load = v out /i lout(max) in and g m = 3s. in a current-mode step-down converter, the output capacitor, its esr, and the load resistance introduce a pole at the following frequency: pmod out load 1 f 2c r = the output capacitor and its esr also introduce a zero at: zmod out 1 f 2 esr c = when c out is composed of n identical capacitors in parallel, the resulting c out = n o c out(each) , and esr = esr (each) /n. note that the capacitor zero for a parallel combination of alike capacitors is the same as for an individual capacitor. the feedback voltage-divider has a gain of gain fb = v fb /v out , where v fb is 1v (typ). the transconductance error amplifier has a dc gain of gain ea(dc) = g m , ea o r out,ea , where g m,ea is the error amplifier transconduc - tance, which is 700s (typ), and r out,ea is the output resistance of the error amplifier 50m. a dominant pole (f dpea ) is set by the compensation capacitor (c c ) and the amplifier output resistance (r out,ea ). a zero (f zea ) is set by the compensation resistor (r c ) and the compensation capacitor (c c ). there is an optional pole (f pea ) set by c f and r c to cancel the output capacitor esr zero if it occurs near the crossover frequency (f c ), where the loop gain equals 1 (0db)). thus: dpea c out,ea c zea cc pea fc 1 f 2 c (r r ) 1 f 2c r 1 f 2c r = + = = the loop-gain crossover frequency (f c ) should be set below 1/5th of the switching frequency and much higher than the power-modulator pole (f pmod ): sw pmod c f ff 5 << figure 4. compensation network r2 r1 v ref v out r c c c c f comp g m maxim integrated 14 www.maximintegrated.com max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi
the total loop gain as the product of the modulator gain, the feedback voltage-divider gain, and the error amplifier gain at f c should be equal to 1. so: cc fb mod(f ) ea(f ) out v gain gain 1 v = ea(fc) m, ea c pmod mod(fc) mod(dc) c gain g r f gain gain f = = therefore: fb mod(fc) m,ea c out v gain g r 1 v = solving for r c : out c m,ea fb mod(fc) v r g v gain = set the error-amplifier compensation zero formed by r c and c c (f zea ) at the f pmod . calculate the value of c c a follows: c pmod c 1 c 2f r = if f zmod is less than 5 x f c , add a second capacitor, c f , from comp to gnd and set the compensation pole formed by r c and c f (f pea ) at the f zmod . calculate the value of c f as follows: f zmod c 1 c 2f r = as the load current decreases, the modulator pole also decreases; however, the modulator gain increases accordingly and the crossover frequency remains the same. pcb layout guidelines careful pcb layout is critical to achieve low switching losses and clean, stable operation. use a multilayer board whenever possible for better noise immunity and power dissipation. follow these guidelines for good pcb layout: 1) use a large contiguous copper plane under the ic package. ensure that all heat-dissipating components have adequate cooling. the bottom pad of the ic must be soldered down to this copper plane for effective heat dissipation and for getting the full power out of the ic. use multiple vias or a single large via in this plane for heat dissipation. 2) isolate the power components and high current path from the sensitive analog circuitry. doing so is es - sential to prevent any noise coupling into the analog signals. 3) keep the high-current paths short, especially at the pgnd ground terminals. this practice is essential for stable, jitter-free operation. the high-current path composed of the input capacitor, high-side fet, inductor, and the output capacitor should be as short as possible. 4) keep the power traces and load connections short. this sudfwlfhlvhvvhqwldoirukljkhiflhqf8vhwklfnfrsshu 3%vryvrwrhqkdqfhixooordghiflhqf 5) the analog signal lines should be routed away from the high-frequency planes. doing so ensures integrity of sensitive signals feeding back into the ic. 6) the ground connection for the analog (agnd) and power (pgnd) section should be close to the ic. this keeps the ground current loops to a minimum. in cases where only one ground is used, enough isolation between analog return signals and high power signals must be maintained. maxim integrated g 15 www.maximintegrated.com max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi
ordering information/selector guide + denotes a lead(pb)-free/rohs-compliant package. *ep = exposed pad. package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos package type package code outline no. land pattern no. 16 tqfn-ep t1655+4 21-0140 90-0121 16 tssop-ep u16e+3 21-0108 90-0120 part v out spread spectrum temp range pin-package adjustable (fb connected to resistive divider) (v) fixed (fb connected to bias) (v) max17245etera+ 1 to 10 5 off -40c to +85c 16 tqfn-ep* max17245eterb+ 1 to 10 3.3 off -40c to +85c 16 tqfn-ep* max17245etesa+ 1 to 10 5 on -40c to +85c 16 tqfn-ep* MAX17245ETESB+ 1 to 10 3.3 on -40c to +85c 16 tqfn-ep* maxim integrated 16 www.maximintegrated.com max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi
revision history revision number revision date description pages changed 0 4/16 initial release ? 2016 maxim integrated products, inc. 17 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max17245 3.5vC36v, 3.5a, synchronous buck converter with 28a quiescent current and reduced emi for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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